| Name | Version | Summary | date |
|---|---|---|---|
| magia-hdl | 0.5.0 | Magia generates Synthesizable SystemVerilog in pythonic syntax | 2024-02-20 20:35:45 |
| magia-ip | 0.0.1 | IP libraries designed with Magia | 2024-02-18 21:21:15 |
| syn-magia | 0.3.0 | Magia generates Synthesizable SystemVerilog in pythonic syntax | 2024-01-06 20:57:03 |
| edg | 0.0.1 | Hardware description language for circuit boards | 2023-05-08 04:12:32 |
| hour | day | week | total |
|---|---|---|---|
| 133 | 1570 | 10478 | 210486 |